The present invention generally relates to gate dielectrics of field effect transistors, and particularly to methods of forming a gate dielectric using a cyclical physical vapor deposition (PVD) process.
Metal-oxide-semiconductor (MOS) technology is a commonly used technology for fabricating field effect transistors (FETs) as part of advanced integrated circuits, such as CPUs, memory, and storage devices, and the like. In MOS technology, a FET may be formed by depositing a gate structure over a channel region connecting a source and a drain. For planar FETs, the channel region is formed in a semiconductor substrate on which the gate structure is formed. In finFETs, the gate structure may be formed over or around a semiconductor fin or fins on an insulator layer, with a source and a drain formed on opposite ends of the semiconductor fin(s).
In MOS technology, the gate structure may be made of a gate dielectric and a gate electrode. In traditional MOS-FETs, the gate dielectric consists of a silicon oxide layer intended in part to prevent current from leaking from the gate electrode into the channel. However, as the critical dimensions of modern microelectronic structures continues to decrease, silicon oxide gate dielectrics may not be reliably used as gate dielectrics due in part to fabrication limits. Therefore, an increasing trend in microelectronic device fabrication is to at least partially replace the silicon dioxide gate dielectric with a high-k dielectric, such as, strontium titanium oxide, hafnium oxide, hafnium silicon oxide, aluminum oxide or zirconium oxide. These high-k dielectrics may be reliably fabricated with thicknesses much greater than a silicon dioxide layer while maintaining approximately the same ability to prevent leakage.
Typically, high-k dielectrics are formed using atomic layer deposition (ALD). However, ALD has a number of disadvantages compared to PVD, potentially including lower growth rate, greater concentration of impurities, and cost of ownership. However, PVD of a high-k dielectric often results in trapped charges within the dielectric layer. Therefore, a process of forming a high-k dielectric layer using PVD that reduces the likelihood of trapped charges is desirable.